library verilog;
use verilog.vl_types.all;
entity mips_datapath is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        RegDst          : in     vl_logic;
        RegWr           : in     vl_logic;
        ExtOp           : in     vl_logic_vector(1 downto 0);
        nPC_sel         : in     vl_logic_vector(1 downto 0);
        ALUctr          : in     vl_logic_vector(1 downto 0);
        MemtoReg        : in     vl_logic;
        MemWr           : in     vl_logic;
        ALUSrc          : in     vl_logic;
        j_sel           : in     vl_logic;
        Instruction     : out    vl_logic_vector(31 downto 0)
    );
end mips_datapath;
